Research

MIPI CPHY is gaining traction on AR and VR prototyping and production devices. Its applications include but are not limited to Simultaneous Locating and Mapping (SLAM), Mixed Reality (MR) pass through cameras, depth sensing and display. Thanks to CPHY's advanced coding scheme that enables 2.28 bit per symbol, lower pin count with smaller PCB area, better power consumptions per bit, and EMI advantages. These prototyping and production devices might consist of multiple rigid-flex PCBs, micro-coax cables, connectors, and other passive and active components, which degrade link signal integrity (SI) even at a relatively low baud rate. As a result, it is critical to understand how sensitive CPHY high-speed signal waveform and link margin to the key system design parameters are, such as I/O parasitic capacitance, jitter, rise/fall time, and channel. Unfortunately, above mentioned parameter information is not always completely available. This paper explores a SI virtuous cycle workflow to fill the gap. The proposed SI workflow significantly improved the measurement to simulation correlation in terms of eye margin, jitter, and transition density, hence further enhances pre-layout simulation accuracy and predictivity for the current design cycle and new products.